The role
From Nvidia's own posting.
NVIDIA is seeking an experienced ASIC Floorplan Engineer to design and implement the world's leading SOCs, CPUs, and GPUs. This position offers you a unique opportunity to craft and to influence the design and development of the next generation GPU and SoC from early architecture development phase through physical design phase, allowing you to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of exceptional people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing.
What you will be doing:
From the early chip definition phase you will partner closely with a wide variety of multi-disciplinary teams starting including product managers, chip architects, ASIC design, physical design, packaging teams among others to craft the chip floorplan that optimizes cost/area, performance, and power for a target market
Drive the floorplan development and collaborate with the ASIC and Physical design teams to identify and solve area, interconnect, timing, and floorplan improvement opportunities to achieve optimal product features and cost
Develop AI workflows and productivity tools to continually improve existing infrastructure for optimizing chip area and speed of execution
Identify key technical and product risks and work with engineering and management teams to close on risk mitigation strategies among the options
What we need to see:
MSEE/MSCE (or equivalent experience) with broad and deep experience in chip development
10+ years of experience
Experience with developing SOC, CPU, graphics, memory, and I/O sub-systems in the chip
Ability to multi-task effectively across simultaneous projects and drive the resolution of complex technical issues among multi-disciplinary engineering teams
Experience with physical design methodologies (flow and tools development), chip floorplan, power/clock/reset distribution, DFT, place and route, timing closure, and packaging
Strong written, verbal, and technical communications skills to present the progress and options to drive towards alignment across many multi-disciplinary teams
Agentic AI workflows, Python, Perl and/or C++ programming language experience
Ways to stand out from the crowd:
Experience in driving development of large scale ASIC floorplans for chiplet based SOC and/or CPU projects
Strong algorithm development and programming skills
Ability to operate optimally in environments with incomplete data, evolving requirements, and tight schedules
NVIDIA is widely considered to be one of the technology world’s most desirable employers. Our products are leading the way with groundbreaking developments in Artificial Intelligence, Autonomous Driving, High-Performance Computing and Visualization. We have some of the most forward-thinking and hardworking people in the world working for us. Are you creative and autonomous? Do you love the challenge of crafting the fastest and most power efficient chips in their class? If so, we want to hear from you.
Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 196,000 USD - 310,500 USD.
You will also be eligible for equity and benefits .
Applications for this job will be accepted at least until October 18, 2026.
This posting is for an existing vacancy.
NVIDIA uses AI tools in its recruiting processes.
NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.