The role
From Marvell Semiconductor's own posting.
About Marvell
Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
Your Team, Your Impact
AI at hyperscale is an architecture problem. Training a frontier model across hundreds of thousands of XPUs, routing over 100 terabits of traffic through a single switch fabric at ~400 nanoseconds of latency, processing optical signals at 1.6T across a data center floor — none of it works without the systems architects, DSP engineers, and algorithm designers who define how data moves, how signals are processed, and how compute is organized at every layer of the stack. At Marvell, that work happens across the full AI interconnect hierarchy: scale-up networks connecting XPUs within a rack using PCIe, UAL, and NVLink-compatible switching; scale-out fabrics interconnecting thousands of XPUs across rows and data center floors through the Teralynx Ethernet switch family — purpose-built for AI, now at 102.4 Tbps with ~400ns latency on the T100; and scale-across connectivity linking geographically distributed data centers through coherent DSP and DCI platforms. The architecture decisions made here define what AI infrastructure can do, at what speed, and at what cost.
The work spans multiple disciplines and multiple markets. On the switching side, teams are architecting the next generation of Teralynx switch silicon — designing forwarding pipelines, congestion control algorithms, traffic management systems, and telemetry architectures for AI fabrics running Ultra Ethernet Consortium protocols at 800G and 1.6T. On the DSP side, teams are developing signal processing algorithms for high-speed optical and electrical links across PAM4, coherent, and coherent-lite modulation formats — work that spans data center interconnect, carrier networking, and emerging AI fabric applications. And on the systems side, teams are defining the architecture of custom XPU connectivity platforms, co-packaged optics integration, and the end-to-end connectivity stack that hyperscalers depend on to scale their AI infrastructure.
Marvell's Ph.D. Intern Program places doctoral candidates directly inside these active architecture and research efforts. Projects are selected because they sit at the intersection of Marvell's most pressing systems-level challenges and the computer architecture, signal processing theory, and networking algorithms that define doctoral research in electrical engineering and computer science. The work is the applied dimension of the academic research a Ph.D. candidate is already pursuing — conducted at production scale, against real system constraints, for hyperscale customers building the world's most advanced AI infrastructure. What you will take away is something no simulation or academic dataset can replicate: the experience of seeing your architectural decisions and algorithms deployed in silicon running inside the world's largest AI data centers.
What You Can Expect
As our Ph.D. Architecture, DSP & Systems Intern, every day you will work on systems-level problems that sit at the boundary of research and production — where the algorithms and architectures you develop have direct consequences for how AI infrastructure performs at scale. Specifically, you can expect to:
Architect, model, and evaluate system-level designs for switching, interconnect, or DSP applications — developing analytical models and simulations that inform real silicon architecture decisions
Develop and optimize DSP algorithms for high-speed electrical or optical links, including equalization, FEC, timing recovery, and signal integrity techniques for PAM4, coherent, or emerging modulation formats
Design and analyze network architectures for AI fabrics — including forwarding pipeline design, congestion control, traffic management, and load balancing for scale-up, scale-out, and scale-across applications
Collaborate with analog, digital, and software engineering teams to validate architectural assumptions against real hardware and silicon measurements
Build behavioral models and simulations in MATLAB, Python, or C++ to evaluate performance tradeoffs across architecture, power, latency, and bandwidth
Present architectural proposals and algorithm results to engineering leadership and contribute to internal technical documentation and design reviews
What We're Looking For
To thrive in this role, you must have hands-on research experience in computer architecture, DSP, or networking systems — with the ability to move fluidly between theory and implementation. Specifically:
Currently enrolled in a Ph.D. program in Electrical Engineering, Computer Engineering, Computer Science, or a related field, with a research focus in computer architecture, digital signal processing, communications systems, or networking
Demonstrate research experience in one or more of the following: processor or switch architecture, DSP algorithm design for high-speed communications, network protocol design, or system-level modeling and simulation
Apply strong analytical fundamentals — whether in signal processing theory, queuing theory, information theory, or computer architecture — to real engineering problems with measurable performance targets
Model and simulate complex systems using tools such as MATLAB, Python, or C/C++; familiarity with hardware description languages (Verilog, SystemVerilog) or cycle-accurate simulation is a plus
Communicate architectural decisions and algorithm tradeoffs clearly — you will present your work to engineering teams and defend your approach against real system constraints
Preferred Qualifications
Familiarity with Ethernet switching architectures, programmable forwarding pipelines, or network congestion control algorithms for large-scale AI fabrics
Experience with PAM4, coherent, or high-speed serial link DSP — including equalization, FEC, or timing and synchronization algorithms
Exposure to custom compute architecture, SoC design, or XPU/GPU interconnect systems
Knowledge of Ultra Ethernet Consortium (UEC) protocols, RoCE, or RDMA networking for AI workloads
Experience with open networking platforms such as SONiC or P4-based programmable pipelines
Expected Base Pay Range (USD)
31 - 62, $ per hour.
The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.



Additional Compensation and Benefit Elements
Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life’s most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights for our interns: medical, dental, and vision coverage, perks and discounts, robust mental health resources to prioritize emotional well-being, and paid holidays. Additional compensation may be available for intern PhD candidates. We look forward to sharing more with you during the interview process.
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com .
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