Silicon Packaging Design Engineer

Job Details: Job Description: Intel seeks a motivated and innovative Silicon Packaging Design Engineer to join our team, driving the end-to-end development of silicon interposer and bridge designs that define the future of computing and connectivity. As a key contributor to Intel's cutting-edge technology, you will play a pivotal role in bridging silicon and hardware design, optimizing package performance, and delivering high-impact solutions that meet performance, cost, and manufacturability goals. Your expertise will directly contribute to Intel's mission to create world-changing technology that improves lives and connects communities worldwide. Key Responsibilities: - Design and implement physical layout and routing of silicon interposers and embedded bridges. - Perform substrate fit and routing studies to evaluate design tradeoffs in performance, cost, and manufacturability. - Collaborate closely with silicon, technology development and hardware teams to optimize system-level design, including silicon-package-board integration and pinout. - Propose design updates changes for rules and conduct internal and external reviews to ensure design feasibility. - Analyze design data and resolve design rule checks (DRCs) to achieve optimized and manufacturable package designs. - Utilize industry-leading electronic design automation (EDA) tools, including Virtuoso, Innovus, FusionCompiler, ICvalidator, and Calibre, to create robust package layouts. - Document processes and design specifications in the product lifecycle management system to ensure traceability and efficient collaboration. - Conduct reviews with partner teams to close milestone requirements Qualifications: Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications: - Bachelor's degree with 3+ years of experience OR Master's degree with 2+ years of experience in Electrical Engineering, Computer Engineering, or a STEM related field Experience listed above should be in the following: Proficiency in custom layout and Auto-place-and-route EDA tools including Virtuoso, Innovus, FusionCompiler, ICvalidator, and/or Calibre. Experience with silicon physical layout design and development, routing interconnects, and/or review tools. Additionally, the candidate should have at least one of the following: 1+ year of experience with Analog/Mixed Signal fundamentals for signal integrity assessments and I/O fundamentals. 1+ year of experience of Power Distribution and power integrity assessments. 1+ year of experience of reliability requirements for interconnects. Preferred Qualifications: Familiarity with industry-leading silicon physical design methodologies and workflows. Ability to effectively collaborate across multi-disciplinary teams and communicate technical concepts clearly. A passion for innovation, problem-solving, and continuous improvement in a fast-paced environment. Prior experience in optimizing silicon performance and conducting tradeoff studies for advanced packaging designs. Join Intel and become an integral part of shaping tomorrow's technology today. Apply now to seize the opportunity to innovate, lead, and create meaningful impact on a global scale Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location: US, Arizona, Phoenix Additional Locations: US, Oregon, Hillsboro Business group: Intel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while delighting our customers -- from delivering cutting-edge silicon process and packaging technology leadership for the AI era, enabling our customers to design leadership products, global manufacturing scale and supply chain, through the continuous yield improvements to advanced packaging all the way to final test and assembly. We ensure our foundry customers' products receive our utmost focus in terms of service, technology enablement and capacity commitments. Employees in the Foundry Technology Manufacturing are part of a worldwide factory network that designs, develops, manufactures, and assembly/test packages the compute devices to improve the lives of every person on Earth. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel . Annual Salary Range for jobs which could be performed in the US: $105,650.00-200,340.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. Work Model for this Role This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change. * ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.