Software Engineer II - Clock Tree Synthesis (CTS), Innovus R&D

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Job Title: Software Engineer – Clock Tree Synthesis (CTS), Innovus R&D Location: Cambridge, UK Reports to: Sr Software Architect Job Overview: This is an early-career software engineering role within Cadence’s Innovus R&D team, focused on Clock Tree Synthesis (CTS) - a core component of physical chip design that directly influences chip performance and power efficiency. You will contribute to the development and improvement of high-performance EDA algorithms while exploring innovative AI-driven approaches to design automation. Working alongside a collaborative, global team in Cambridge, you will be supported by strong mentorship as you grow your technical depth and make a meaningful contribution to industry-leading chip design tools. Job Responsibilities: Design and implement EDA algorithms: Build and refine CTS algorithms in C/C++, with a focus on performance, quality of results (QoR), scalability, and correctness across diverse chip design scenarios. Debug, optimise, and enhance CTS capabilities: Identify and resolve performance bottlenecks and robustness issues within the Innovus platform, improving reliability and runtime efficiency. Develop AI-driven and automated workflows: Apply emerging agentic and data-driven approaches to explore design trade-offs, reduce manual effort, and improve the adaptability of physical design flows. Explore adaptive techniques for physical design: Investigate and prototype data-informed methods that improve tool reliability and design outcomes across varying chip architectures. Collaborate with global R&D teams: Partner with engineers and researchers across Cadence’s worldwide offices to align on technical direction, share findings, and contribute to roadmap development. Communicate technical work clearly: Document algorithms, design decisions, and experimental findings through code reviews, written summaries, and team discussions. Stay current with the field: Actively engage with advances in algorithms, AI/ML, and EDA research to bring new thinking into the team’s work. Job Qualifications: MSc in Computer Science, Electrical Engineering, or a related numerate discipline - or equivalent practical experience in a relevant technical field. Strong programming skills in C/C++, developed and applied in a Linux or Unix-like environment. Solid understanding of core data structures and algorithms, with the ability to analyse and reason about algorithmic complexity. Effective problem-solving approach, with the ability to break down complex technical challenges and communicate findings clearly to colleagues. Additional Skills/Preferences: The following are not required, but would be a welcome addition: Exposure to AI/ML techniques, optimisation methods, or automated decision-making systems. Familiarity with EDA concepts such as timing analysis, clock tree synthesis, or physical design flows. Experience with multi-threaded or parallel programming in performance-critical environments. Curiosity about the behaviour and improvement of large-scale software systems. Demonstrated interest in learning new tools, techniques, or problem domains — through personal projects, research, or coursework. Additional Information: This role is based in Cadence’s Cambridge, UK office, within the Innovus R&D team - a technically rich environment where researchers and engineers collaborate closely on some of the most complex problems in chip design. The team is global, and you will have regular opportunities to work with colleagues across different geographies and disciplines. The Innovus platform is used by many of the world’s foremost chip designers, and your contributions will have real impact on a product at the heart of modern semiconductor design. This role is well-suited to someone early in their career who is eager to develop deep expertise in algorithms and AI-driven design, supported by dedicated mentorship and a culture that values technical curiosity and continuous learning. Key tools and environments include: C/C++, Linux/Unix systems, and the Innovus EDA platform. Familiarity with version control and software engineering best practices is expected. Check what we can offer you: Competitive salary 25 days holiday per year Private Medical and Dental plans, Income Protection and Life Insurance Group Personal Pension Plan Cycle to work scheme and gym subsidy 5 days paid time to volunteer to give back to our communities Employee Stock Purchase Plan The opportunity to work for a Great Place to Work© & Fortune 100 organization Cadence is committed to equal employment opportunity and employment equity throughout all levels of the organization. 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