At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
The candidate will have the opportunity to work on many varieties of challenging designs, i.e. low power and high speed design. As well as participating in or leading next generation PHY IP physical design, methodology and flow development, the candidate will work closely with our RTL design team & Analog Team to ensure successful tapeouts.
Main Job Tasks and Responsibilities:
-Participating in or leading next-generation physical design, methodology, and flow development in advanced technology nodes.
-Perform physical design implementation, including floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, physical verification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure.
Position Requirements:
- Bachelor or above degree in majors of EE/CS/IT, with 3+ years work experience
- Extensive knowledge of the design rule for the process of N7/N5 and below
- Knowledge of scripting languages and use in methodology
- Ability of fixing the physical design violations, including: DRC, DFM, LVS, ANT, ERC etc.
- Deep experience of static timing analysis
- Ability to learn quickly
- High level of communication and teamwork
- Carefulness, responsibility, and persistence
We’re doing work that matters. Help us solve what others can’t.
We welcome applications from candidates with disabilities and in equity seeking groups. If you have accessibility needs during the application and interview process, we encourage you to make your needs known.